1. Field
The present disclosure pertains to the field of information processing, and more particularly, to the field of managing interrupts in information processing systems.
2. Description of Related Art
Many personal computer and other information processing systems manage interrupts according to Intel® Corporation's Advanced Programmable Interrupt Controller (“APIC”) architecture or an interrupt architecture based on the APIC architecture. One or more processors in such a system may include a local APIC, and the system may include one or more input/output (“I/O”) APICs. An I/O APIC may be integrated with or into another system component, such as a memory controller, a bus controller, or an I/O controller. An I/O APIC may communicate with local APICs through messages on the bus or other interface between the processors and memory, and/or through a dedicated APIC bus or other interface.
The hardware for an I/O APIC includes storage for a set of programmable registers along with state machines to control storage and processing of register values. Two of the registers of the I/O APIC, namely the I/O register select (“IOREGSEL”) register and the I/O window (“IOWIN”) register, are directly accessible through memory mapped I/O transactions, while the others are indirectly accessible using an index value from the IOREGSEL register and a data value from the IOWIN register. Typically, the addresses for the IOREGSEL and IOWIN registers are FEC00000h and FEC00010h, respectively, but these registers may be relocated. The register set also includes twenty-four redirection registers, each having a width of sixty-four bits, collectively referred to as the redirection table. Each of these registers corresponds to one of twenty-four interrupt request inputs to the I/O APIC. The format of a redirection table entry (“RTE”) includes a field to store an eight-bit interrupt vector, which is sent to the processor(s) with the corresponding interrupt request. The processor uses the interrupt vector to identify an entry in the interrupt descriptor table, from which the interrupt handler may be found.